AspeQt for OSX

2 years ago i started to transfer my old Atari 800 XL software from the 28 years old “5,25 disk to ATR images on my laptop. But i was never happy with the setup using a windows program in a vm to do the transfer. I found AspeQt which is opensource, but it did not support OSX. So i started to add an serial driver with OSX support to it. And then forget about it. Till recently when i got an email from the AspeQt maintainer Ray who asked about the state of my github repo. Since i want OSX support in the mainline, i picked the lastest version of AspeQt to update my repo, which already got a little stale. Then i found out that is a pain in the ass to run QT4.8 on Maverick, there is no offical package and building from source you end up in patch hell.

So i decided to move my branch of AspeQt to QT5.2, which was pretty straight forward.

QtCreator is not a great editor but does the job

QtCreator

QtCreator

AspeQt on OSX

AspeQt on OSX

AspeQt on OSX

Found some cool stuff on my disks

Software from the 80ies

Software from the 80ies

Meet my new project Userlike

Its not that i have been kind of lazy about blogging the last year, its just i didn’t to anything on my side projects like SNES hacking or the like. I quit my day job last year and started founding my own Company Devcores. Last Summer i began coding our first SAAS wich entered the beta phase last december. Lets meet Userlike. It’s a webbased live chat system targeted for online shops. It SAAS and can be added with one line of javascript to your website. We are in private beta right now and plan to release the first public version with the next 2 month. If you want to test it, drop me a line and i will get you an account.

Userlike

Quickdev2 Progress

After building the quickdev16 in the summer of 2010 we decided to work on a 2nd version off the quickdev16, which we called quickdev2. All this work was done in the summer of 2010 but i never got around to finish the project nor to blog about it. So here is a little overview:

The next quickdev should be a little bit faster and should have more features. So we selected a new CPU, the Atmel at90usb1287 that can handle USB via hardware and has more SRAM. To simplify the logic part we opted for a XILINX CPLD xc95144xl. We used a bigger Cypress 16-Mbit SRAM CY62167E. The AVR would expose the USB interface to the PC side, as a masstorage device using the LUFA library. The AVR has a data bus to the CPLD. The CPLD is also connected to the external SRAM. In the CPLD we implemented a SREG, counter, commandmuxer and memory interface in Verilog.

The system top looks like this:

module system (

    inout [7:0] sram_data,
    output [20:0] sram_addr,
    output sram_oe_n,
    output sram_we_n,
    output sram_ce_n,


    output [7:0] snes_data,
    input [20:0] snes_addr,

    inout [7:0] avr_data,
    input [7:0] avr_ctrl,
    input avr_clk,
    output [7:0] debug
);

We have a 8 bit data bus and 21 bit address bus to the SRAM. 3 extra lines for OE,WE and CE. Then there is the same setup for the SNES side. 8 Data and 21 address line. No more control lines to the SNES are currently implemented. There is a 8 bit data and 8 bit control bus to the AVR. Finally we have a CLK line from the AVR to the CPLD and a 8bit debug bus. The AVR clocks its own clock into the CPLD, which is feed into a DCM and is divided by 2. This clock signal is feed into the FSM and SREG internally. The avr_ctrl bus is feed into a commandmuxer which drives the other components on the CPLD. Foremost it drives a FSM which manages the data routing between AVR <-> SRAM and SRAM <-> SNES.

module bus_fsm #(
    parameter DWIDTH = 8
)(
    input                   clk,
    input                   reset,
    input                   we_n,
    input                   oe_n,
    inout   [DWIDTH-1:0]    avr,
    inout   [DWIDTH-1:0]    sram,
    inout   [7:0]           debug
);

parameter SIZE   =  3;
parameter IDLE    = 3'b000;
parameter WE      = 3'b001;
parameter BUFAVR  = 3'b010;
parameter BUFSRAM = 3'b011;
parameter OE      = 3'b100;


reg   [SIZE-1:0]          state;
reg   [SIZE-1:0]          next_state;
reg   [DWIDTH-1:0]        buffer_avr;
reg   [DWIDTH-1:0]        buffer_sram;
reg   [DWIDTH-1:0]        buffer;

assign avr = buffer_avr;
assign sram = buffer_sram;

always @ (state or we_n or oe_n)
begin : FSM_COMBO
    next_state = 3'b000;
    case(state)
    IDLE : if (we_n == 1'b0) begin
            next_state = BUFAVR;
        end else if (oe_n == 1'b0) begin
            next_state= BUFSRAM;
        end else begin
            next_state = IDLE;
        end
    BUFAVR: if (we_n == 1'b0) begin
            next_state = WE;
        end else begin
            next_state = IDLE;
        end
    BUFSRAM: if (oe_n == 1'b0) begin
            next_state = OE;
        end else begin
            next_state = IDLE;
        end
    OE : if (oe_n == 1'b0) begin
            next_state = BUFSRAM;
        end else begin
            next_state = IDLE;
        end
    WE : if (we_n == 1'b0) begin
            next_state = BUFAVR;
        end else begin
            next_state = IDLE;
        end
  endcase
end

//----------Seq Logic-----------------------------
always @ (posedge clk)
begin : FSM_SEQ
    if (reset == 1'b1) begin
        state < = #1 IDLE;     end else begin         state <= #1 next_state;   end end  //----------Output Logic----------------------------- always @ (state) begin : OUTPUT_LOGIC   case(state)     IDLE: begin         buffer_avr <= 8'bz;         buffer_sram <= 8'bz;         buffer <= 8'bz;     end     WE: begin         buffer_sram <= buffer;     end     OE: begin         buffer_avr <= buffer;     end     BUFSRAM : begin         buffer <= sram;     end     BUFAVR : begin         buffer <= avr;     end     default : begin         buffer_avr <= 8'bz;         buffer_sram <= 8'bz;     end   endcase end  assign debug = { clk,we_n,oe_n,state,2'bz}; endmodule 

From the AVR software side a SRAM write looks like this.


void sreg_set(uint32_t addr)
{


    uint8_t i = 21;
    #if SREG_DEBUG 
    uart_putstring("sreg_set\n\r");
    #endif
    SET_AVR_SREG_EN_HI();
    while(i--) {
        if ((addr & ( 1L < < i))){             SET_AVR_SI_HI();     #if SREG_DEBUG              uart_putchar('1');     #endif         } else {             SET_AVR_SI_LO();     #if SREG_DEBUG              uart_putchar('0');     #endif         }         SET_AVR_SREG_EN_LO();         SET_AVR_SREG_EN_HI();     }     #if SREG_DEBUG      uart_putstring("\n\r");     #endif }  void SRAM_write(uint32_t addr, uint8_t data) {      // set direction of data port     AVR_DATA_DIR = 0xff;     // load address     sreg_set(addr);     // disable OE and WE     SET_AVR_OE_HI();     SET_AVR_WE_HI();     // wait for FSM to go into IDLE state     nop();     nop();     // write data     AVR_DATA = data;     // enable WE     SET_AVR_WE_LO();     // wait for FSM to go into WE state     nop();     nop();     nop();     nop();     // disable WE     SET_AVR_WE_HI(); }  

The development was done on our new prototype board, which Max layouted for us. I used an AVR Dragon for the AVR programming part and debugging via JTAG. For the CPLD side i used a homebrew Xilinx Platform cable alongside with ISE. I quickly stopped using the IDE and just cooked my own Makefile using the Xilinx commandline tools.

Most of the logic was developed using a testbench and running through iverilog. But having a module working in a testbench doesn't mean that it works on real hardware. We had todo a lot of debugging on the real hardware. This involved a lot of test probe soldering. Luckily we had my 8bit Saleae LA which helped a lot to track done some Problems. But the biggest issue was to get the timing right with the FSM for the memory bus.

We hacked this in a 3 day weekend sprint and implemented the SRAM read and write from the AVR side. But then we hit a wall and didn't implement the SNES side. The project lost some traction. Max had moved to Berlin we couldn't work together on the project anymore. We lost a little interest because the sd2snes project achieved what we we intended to do and Ikari_01 did far better job then we did. I recently got word the sd2snes is considered stable and a first batch is sold.

We plan to start working on this again. To implement the SNES side of the memory we would need to increase the speed of the FSM to get it into IDLE state and then in SNES state within 120ns or 200ns after the SNES does a CS on the cartridge. Since the AVR drives the CPLD clock with 20MHz, we would need some kind of PPL to run the FSM with like 60MHz, which should be plenty to run the FSM for the SNES SRAM read.

We appreciate any comment or suggestion for the hardware design of this project.

Super Nintendo Talk

A while ago i held a talk at the ccc in cologne about my favorite game console the Super Nintendo. This talk covers the Super Nintendo technology in detail. Starting with the CPU and PPU, covering the cartridge memory maps and showing most of the custom chips which where used on cartridges. I also show development hardware, copier stations and the current available flashcarts. The topic emulation is also covered . The second part of the talk is about the quickdev16 project, which i did with my friend max in 2009. We built a flashcart for the SNES which is useful for developing homebrew software. The talk sums up all the details i learned during the research i made to built this kind of cartridge. I uploaded the slides, maybe someone find this useful to dive into the SNES world.

Memory Visualizer for BSNES

Some time ago i saw this Memory Visualizer for Frodo and Vice C64 Emulator . I got inspired to do something simular for the SNES. I took this idea an hacked it right into BSNES. Right now i have 2 fields representing the WRAM and the VRAM of the SNES. So it displays different colors for read and write access to the memory areas. Due fading this generates some color blending effects. This is just a quick hack which was lying on my hd for some months. So its based BSNES version 0.59 , which is know a little outdated. It would need some more polishing and a better solution to display the 2 Ram areas. The GL cubes look a little lame. Also the emulator performance is not quite there so that the roms a little bit slow.

[flash]http://vimeo.com/11400325[/flash]

Download Video

New Quickdev16 Loader

We got a new loader for the Quickdev16 firmware. The loader will replace the current dummy loader and has a few new advantages:

qd16boot02

  • Faster upload because of IRQ driven communication between SNES and AVR
  • Progressbar while uploading
  • Display Rom infos
  • ASCII and Katakana font support
  • Eyecandy: new logo design with sine wave effect and bassdrum synced background effects..

Due to these features the loader blew up to more than 55kb, too much for our limited space in the AVR progmem (64kb – 4kb bootloader). Our main firmware is between 8kb and 24kb, depends on the debug-features that you compile in. So the recent task is to either reduce the loader size by skipping eyecandy, finding a better compression routine to compress it in the progmem or build a minimal firmware and put parts of the loader into the surplus 4kb eeprom on the AVR. Probably we will have to combine the different approaches.

One reason why the firmware is that big these days is the new “minimal debug terminal”, a serial command line where you can maintain the Quickdev system status. You can dump memory regions from sram, switch between the busses, write to the shared memory section, show the status of the hardware ports and use several other usefull commands. Check the project page for more details on the commands.

Quickdevs are shipping

Last week we shipped the first batch of Quickdevs. The Software is feature ready, but we wanted to do some eye candy on the SNES software side, which didn’t work out yet. So software updates are coming within the next weeks.

Feel free to order at david @ optixx.org.

First Quickdev16 PCB is working

Not “out of the box” but with only slightly changes on the software part, the new quickdev16 PCBs are working. Their shape fit the SNES cartslot, the changes in hardware design and parts worked out great and we have a kind of stable firmware and upload tool.

When you turn on the SNES, the microcontroller extracts a small loader-rom into the cartridge RAM that is mapped into the SNES addressspace. This one copies itself to SNES’s WRAM and jumps into it. So the cartridge RAM is unaccessed and we can safely switch back to the AVR mode to push a real payload rom onto the cartridge. We are also working on a shared memory function so that we can use the cartridge RAM to exchange infomation between the AVR and the SNES. This will be used to display a proper Progressbar while uploading a rom.

As usal you can use our patched version of ucon64 – even under windows – to upload a game to the quickdev16. When the upload is done, the SNES reset line is pulled by quickdev16 and the game starts. When you press the reset button, you only reset the game, not the quickdev16 – it acts like a normal cart. When you press the reset button during the upload process or while watching the loaderscreen, you reset the quickdev and can abort uploads or just restart the quickdev16 – thats a really usefull feature. To initiate the upload of a new game, just start the upload process with ucon, the quickdev switches to the loader mode by itself and receives the new ROM.

So the steps are now to improve the loader code, finish the progress bar stuff, figure out how to solder the PCBs faster than now and add some minor features. Stay tuned for updates, it’s not too long to the release.

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